High-Performance Chemical Mechanical Planarization for Advanced Memory Manufacturing

Chemical Mechanical Planarization (CMP) has evolved from a niche planarization technique into a cornerstone of modern semiconductor manufacturing. As memory devices transition to vertically stacked architectures—3D NAND with hundreds of active layers and High-Bandwidth Memory (HBM) requiring ultra-smooth bonding interfaces—the demands on CMP materials and processes have intensified dramatically.

With the continued scaling-down of semiconductor devices, achieving both low surface roughness and high polishing rate during silicon CMP is becoming increasingly critical, especially for HBM and 3D NAND applications . These advanced architectures require ultra-smooth, defect-free surfaces for reliable die-to-die bonding and precise mask alignment in subsequent lithography steps 

1. The CMP Challenge in Advanced Memory

1.1 3D NAND Requirements

3D NAND flash memory stacks 200+ layers of word lines and insulating films. The staircase structure—where word line contacts are formed at each layer—requires exceptional surface planarity to ensure proper contact formation .

Key CMP Challenges:

• Polishing of high-aspect-ratio structures without dishing

• Maintaining selectivity between multiple film types (oxide, nitride, polysilicon)

• Achieving sub-nanometer surface roughness for subsequent deposition

1.2 HBM Requirements

HBM uses through-silicon vias (TSVs) and micro-bumps to stack multiple DRAM dies. The bonding interfaces must be atomically smooth—surface roughness below 0.10 nm is required for reliable hybrid bonding .

Key CMP Challenges:

• Final touch CMP of silicon surfaces for die-to-die bonding

• Polishing rates exceeding 200 Å/min with surface roughness below 0.10 nm

• Elimination of CMP-induced defects (particles, scratches) 

1.3 Memory Device Trends Driving CMP Evolution

• Novel transistor structures: Gate-All-Around (GAA), 3D NAND, and HBM require new CMP processes and slurry formulations 

• Shift to lower abrasive content: The industry is focusing on chemical components of CMP, with reduced abrasive concentration 

• Increased CMP steps: Rising chip integration means more CMP steps, increasing importance of post-CMP cleaning and contamination control 

2. Advanced Si CMP Slurry for HBM and 3D NAND Final Touch

2.1 The Scientific Breakthrough

Recent research has demonstrated that advanced Si CMP slurry formulations can simultaneously achieve polishing rates exceeding 200 Å/min and surface roughness below 0.10 nm without CMP-induced defects such as particles and scratches .

Optimized Slurry Composition:

2.2 Working Mechanism

Hydrolysis Reaction Acceleration:

The amine-functional hydrolysis reaction accelerator significantly enhances the hydrolysis of the Si surface by increasing OH⁻ concentration, facilitating the conversion of Si–Si and Si–O–Si bonds to Si–OH . This promotes effective chemical removal of Si atoms, substantially increasing the polishing rate.

However, at higher concentrations, excessive OH⁻ generation causes:

• Particle agglomeration

• Unstable dispersion

• Increased surface roughness

Optimized concentration (0.05–0.20 wt%) achieves: Polishing rates of 250–335 Å/min while maintaining surface roughness below 0.10 nm .

Defect Suppression Additive Role:

The hydroxyl-functional additive primarily influences slurry viscosity and forms a hindrance layer on the Si surface. At low concentrations:

• Moderately increases slurry viscosity

• Facilitates stable abrasive dispersion

• Enables efficient surface contact

At higher concentrations:

• Forms dense hindrance layer through hydrogen bonding with Si–OH groups

• Reduces effective interaction between abrasives and wafer surface

• Lowers polishing rate 

2.3 Abrasive Size Optimization

Abrasive diameter significantly impacts performance:

Key Finding: Proper abrasive sizing is essential to balance surface quality and material removal rate. The combination of ~20 nm colloidal silica abrasives with optimized chemical additives enables high-efficiency polishing with scratch-free surfaces .

3. STI CMP: High Selectivity Shallow Trench Isolation

3.1 STI CMP Requirements

Shallow Trench Isolation (STI) is a critical FEOL process requiring oxide-to-nitride polishing selectivity exceeding 50:1 to stop precisely on the nitride layer without excessive dishing.

Industry Solutions:

Advanced oxide CMP products use ceria abrasive and chemical additive formulation technology to achieve :

• High removal rate

• Best-in-class topography

• Tunable dilution at point of use

• Proven high-volume manufacturing quality consistency

Key Performance Differentiators:

3.2 Selectivity Enhancement Mechanism

High selectivity STI slurries utilize organic compounds that suppress silicon nitride removal while minimally affecting silicon oxide removal .

Selectivity-Enhancing Compounds:

• Sulfates of alcohols (e.g., ammonium lauryl sulfate)

• Sulfonic acids and salts (e.g., dodecylbenzenesulfonic acid)

• Sulfuric acid ether salts

Example Performance:

• Ammonium lauryl sulfate (ALS) at 0.4 wt% achieved oxide:nitride selectivity of 600:1 

• Oxide removal rate: ~2,200 Å/min

• Nitride removal rate suppressed to ~12–17 Å/min

Selectivity Control: The selectivity can be adjusted by controlling pH. Acidic pH (2.0–3.0) gives maximum selectivity; selectivity decreases as pH increases .

Applications:

• FEOL dielectrics (STI P1 and P2 steps)

• Logic and memory (DRAM, NAND, 3D NAND)

• Sensors (MEMS, optoelectronics) 

4. Tungsten CMP for Interconnects

4.1 W CMP Requirements

Tungsten CMP removes excess W deposited for contacts and vias, stopping on barrier layers (TiN, Ti). Critical parameters include :

• Removal rate

• Topography control

• Dishing and erosion minimization

• Low defectivity

4.2 Tunable W CMP Solutions

Product Family Capabilities :

Industry Applications:

• Logic devices

• Memory (DRAM, NAND, 3D NAND)

• Advanced packaging 

Key Differentiators:

• Wide selectivity windows

• Optimal removal rates

• Tunable dilution at point of use

• Cost of ownership optimization

5. Post-CMP Cleaning for Advanced Nodes

5.1 The Contamination Challenge

CMP introduces multiple types of surface contaminants that must be completely removed :

5.2 Cleaning Mechanisms

SC-1 Cleaning and Brush Scrubbing (Particle Removal):

Silica particles undergo a condensation reaction with the wafer surface during CMP, forming Si–O–C bonds on amorphous carbon surfaces .

• SC-1: Breaks Si–O–C through nucleophilic reactions

• Brush scrubbing: Breaks bonds via drag force

• Combined efficiency: >93% particle removal 

SC-2 Cleaning (Metal Ion Removal):
Dissolves metal ions by forming soluble metal chloride complexes (e.g., FeCl₃, CuCl₂) 

SPM Cleaning (Organic Removal):
Sulfuric acid/hydrogen peroxide mixture decomposes polyurethane-based pad debris into small, soluble molecules 

5.3 PVA Brush Contamination Management

PVA brush cleaning is widely used for post-CMP particle removal. However, brushes accumulate slurry particles over time, leading to performance degradation and potential wafer recontamination .

Quantitative Assessment Method:
A spectrophotometry-based method measures absorbance of deionized water after contact with the brush, directly indicating residual slurry particle concentration .

Cleaning Strategy Effectiveness :

Key Finding: Buffing prior to brush contact effectively reduces particle accumulation on brushes and minimizes recontamination risks .

5.4 Emerging Cleaning Technologies

Dynamic Megasonic Cleaning:

Megasonic cleaning is evolving from static to dynamic systems with:

• Flowing cleaning chemistry

• Wafer rotation

• Enhanced particle removal

• Uniform cleaning with reduced reattachment risk 

This approach shows increased particle removal efficiency (PRE) for both TEOS and SiC substrates, with reduced risk of localized cavitation and particle redeposition .

Composite Surfactant Systems:

For advanced metal surfaces (e.g., cobalt interconnects), composite surfactant systems demonstrate superior particle removal :

• Cationic + nonionic surfactant combinations achieve >94% PRE

• Enhanced wettability reduces surface hydrophobicity

• Stronger electrostatic repulsion between particles and surface

• Validated on patterned wafers for practical application

6. Performance Summary

6.1 Key Performance Metrics

6.2 Post-CMP Cleaning Performance